This is an exciting opportunity for a Senior FPGA Designer who would also like to develop their skills in a DevOps position.

We will enable you to be involved in making dramatic changes to the compute and Data Center industry by making a significant contribution to our disruptive next generation solutions for Composable Disaggregated Infrastructure (CDI). Building off our switchless network solutions for systems in High Performance Compute, Data Center, and networked clusters, the CDI space offers new technology advancement opportunities and an avenue to introduce new and efficient concepts into the evolving compute industries.

What you will do

• Develop your skills with Placement, Timing Closure & New Part/Board Setup in Intel Quartus and Agilex based devices
• Work with Hardware design to capture the initial FPGA configuration requirements
• As time permits, be involved in the Design of RTL code for product inclusion
• Develop and maintain Continuous Integration processes for FPGA/ASIC build flows & applications by accessing and using tools like Jenkins, GitHub etc.
• Troubleshoot and triage on the build pipeline, infrastructure and tools issues
• Execute medium to large tasks independently & provide regular updates to stakeholders
• Develop mock-ups or requirement prototypes for features of moderate to high complexity and effectively articulate the requirements to relevant stakeholders

The experience you bring

• A minimum of 6 years experience as an ASIC/FPGA Designer
• A degree in Electrical Engineering or a related field
• Solid experience in Xilinx Vivado FPGA build and release process
• Expertise in operating Linux environment with good command over any scripting language such as Shell, Python, etc.
• Deep experience with Xilinx and Cadence EDA tools
• Experience with simulation, synthesis and backend ASIC tool flow
• Strong hands-on knowledge of Python, Bash, Jenkins, GitHub CI/CD pipeline tools
• Strong troubleshooting and triaging capabilities, passionate to learn & quickly adapt to the new technology, process knowledge.

Bonus if you have

• Knowledge and exposure to Intel FPGA design flow and tools
• Knowledge of protocols related to highspeed, low latency, and switching data path
• Knowledge of ASIC/FPGA verification methodologies such as UVM
• Knowledge of System Verilog
• Experience with low power design techniques, for ASIC/FPGA
• Experience with design optimization for speed/timing, power, area
• Exposure to team lead and team development roles
• Experience with Implementing LSF/Grid like compute framework.